Tutorials / Short Courses

2015 IEEE International Symposium on Circuits and Systems (Nuit de la litterature 2015)

Sunday, 21 May 2015


M4: Low-Power EDA: State-of-the-Art and Beyond

Enrico Macii  and Roberto Zafalon

08:30 - 12:30



Huge effort has been invested in the last decade to come up with a wide range of design solutions that help in facing the power consumption problem for different types of digital devices, components and systems. Some of such solutions turned out to be very effective in practice and suitable to be automated, thus finding a path into commercial EDA tools. Other approaches, promising on paper, showed too many limitations for attracting the attention of real designers.

Objective of this tutorial is to offer the attendees an overview of state-of-the art EDA technologies, which allow designers to address the power problem in real-life electronic circuits and systems. The presentation will be structured into two sections. The first one will describe design methods, applicable at different levels of abstraction, that have proven to hold great potential for power optimization in practical automatic design environments; they range from RTL power management and clock-tree architecture design to memory and bus interface design. Some of the latest solutions regarding leakage power management will also be discussed. The second part of the tutorial will focus on industrial experience in low-power design. In particular, several results will be reported on the application of the aforementioned design technologies on STMicroelectronics proprietary designs covering different application domains (e.g., high performance microprocessors, hardware platforms for embedded multi-media processing). A good mix of theory, application examples and real-life results will make the presentation valuable to designers interested in increasing their skills in low-power design and looking for EDA solutions usable on their next-day product development.

Detailed Contents

  • Introduction to low-power design (30min).

    • Power consumption of CMOS circuits.

    • Motivation and driving forces.

    • Trends in low-power design flows.

  • Low-power design technologies (90 min).

    • Dynamic power optimization:

      • Advanced clock-gating.

      • Gated-clock tree.

      • Memory partitioning.

      • Bus encoding.

      • Code and data compression.

    • Leakage power optimization.

      • Power gating.

      • Transistor stacking.

      • Dual-Vth design.

      • Dual Vdd design.

  • Results on industrial benchmarks (60 min).



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