Tutorials / Short Courses

2015 IEEE International Symposium on Circuits and Systems (Nuit de la litterature 2015)

Sunday, 21 May 2015


A10: Extensible and Configurable Processors for System-on-Chip Design

Jari Nurmi, Steven Leibson, Fabio Campi and Christian Panis

13:30 - 17:30



This tutorial is aimed at researchers and designers involved with complex SOC design who need to understand how to develop complex, mega-gate SOCs under severe time and cost constraints. Managers at companies making significant investments in SOC designs and platforms will also find the information in this tutorial essential to making decisions regarding the changes they may need to make in investment strategies, core competencies, and organization structure over time.

The tutorial outlines the major forces changing today’s SOC design process, and introduces the concept of SOC design using extensible or scalable processors as a basic design fabric. It teaches the essentials of different extensible processor architectures, tools for instruction-set extension and reconfiguration, and multiple-processor SOC architecture for embedded systems. It uses several examples with different flavors of extensibility, scalability and reconfigurability to give a precise, practical, and up-to-date picture of the real issues and opportunities associated with this new design method: Open-source Coffee RISC Core with the coprocessor approach to algorithm acceleration; xDSPcore scalable VLIW DSP approach; Run-time reconfigurable XiRISC core with its Pipelined Configurable Gate Array (PiCo GA); and Tensilica’s extensible Xtensa processor architecture. The associated design tool flows are also introduced.

The tutorial concludes by looking down the road at the longer-term future of SOC design, examining basic trends in design methodology and semiconductor technology. It paints a 10-15 year outlook for the qualitative and quantitative changes in design, in applications, and in the structure of the electronics industry.

Tutorial Outline:

1. The SoC design problems: complexity, change, and risk (Leibson, 30 minutes)

2. Accelerating single-processor cores – a co-processor approach (Nurmi, 30 minutes)


3. Scalable instruction-word VLIW DSP architecture – xDSPcore and design space exploration flow for a scalable processor – DSPxPlore (Panis, 30 minutes)

4. Run-time reconfigurable DSP RISC processor – XiRISC and the Griffy algorithm development suite (Campi, 30 minutes)


5. Extensible RISC processor – Xtensa (Leibson, 30 minutes)

6. The future of SoC design (Leibson, 10 minutes)



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